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freescale semiconductor, inc. reserves the right to change the detail specifications, as may be required, to permit improvements in the design of its products. document number: mpc17531a rev. 4.0, 5/2009 freescale semiconductor technical data ? freescale semiconductor, inc., 2005 - 2009. all rights reserved. 700 ma dual h-bridge motor driver with 3.0 v compatible logic i/o the 17531a is a monolithic dual h-bridge power ic ideal for portable electronic applications c ontaining bipolar step motors and/or brush dc-motors (e.g., cameras and disk drive head positioners). the 17531a operates from 2.0 v to 8.6 v using the internal charge pump, with independent control of each h-bridge via parallel mcu interface. the device fe atures built-in shoot-thr ough current protection and an undervoltage shutdown function. the 17531a has four operating modes: forward, reverse, brake, and tri-stated (high impedance). the 17531a has a low total r ds(on) of 1.2 (max @ 25c). the 17531a efficiently drives many types of micromotors with low power dissipation owing to its low output resistance and high output slew rates. the h-bridge outputs can be independently pulse width modulated (pwm?ed) at up to 200 khz for speed/torque and current control. features ? low total rds(on) 0.8 w (typ), 1.2 (max) @ 25 c ? output current 0.7 a (dc) ? shoot-through current protection circuit ? pwm control input frequency up to 200 khz ? built-in charge pump circuit ? low power consumption ? undervoltage detection and shutdown circuit ? power save mode with current draw 2.0 a ? pb-free packaging designated by suffix codes ev and ep figure 1. 17531a simplified application diagram dual h-bridge vmfp suffix ev suffix (pb-free) 98asa10616d 20-terminal vmfp 17531a ordering information device temperature range (t a ) package mpc17531aev/el -20c to 65c 20 vmfp mpc17531aep/r2 24 qfn qfn suffix ep suffix (pb-free) 98arl10577d 24-terminal qfn cres c1l c1h c2l c2h in2b psave in2a in1a out2b out2a out1b out1a vm gnd mcu in1b 3.0 v 5.0 v 17531a bipolar step motor n s vdd
analog integrated circuit device data 2 freescale semiconductor 17531a internal block diagram internal block diagram figure 2. 17531a simplified internal block diagram vm1 out2b out2a out1a pgnd2 in1a c2h in1b c1h c2l c1l vdd low- shutdown charge level shifter vm2 out1b in2a in2b psave lgnd pgnd1 control predriver pump voltage h-bridge h-bridge logic cres vdd
analog integrated circuit device data freescale semiconductor 3 17531a terminal connections terminal connections figure 3. 17531a, 20-terminal vmfp connections table 1. 17531a, 20-terminal vmfp definitions a functional description of each terminal can be found in the functional terminal description section beginning on page 10 . terminal number terminal name formal name definition 1 vdd logic supply control circuit power supply terminal. 2 in1a logic input control 1a logic input control of out1a (refer to table 6, truth table , page 9 ). 3 in1b logic input control 1b logic input control of out1b (refer to table 6, truth table , page 9 ). 4 psave power save logic input controlling power save mode. 5 out2a h-bridge output 2a output a of h-bridge channel 2. 6 pgnd1 power ground 1 high-current power ground 1. 7 out1a h-bridge output 1a output a of h-bridge channel 1. 8 vm1 motor drive power supply 1 positive power source connection for h-bridge 1 (motor drive power supply). 9 cres predriver power supply internal triple charge pump output as predriver power supply. 10 c2h charge pump 2h charge pump bucket capacitor 2 (positive pole). 11 c1h charge pump 1h charge pump bucket capacitor 1 (positive pole). 12 c1l charge pump 1l charge pump bucket capacitor 1 (negative pole). 13 c2l charge pump 2l charge pump bucket capacitor 2 (negative pole). 14 out1b h-bridge output 1b output b of h-bridge channel 1. 15 pgnd2 power ground 2 high-current power ground 2. 16 out2b h-bridge output 2b output b of h-bridge channel 2. 17 vm2 motor drive power supply 2 positive power source connection for h-bridge 2 (motor drive power supply). 18 in2b logic input control 2b logic input control of out2b (refer to table 6, truth table , page 9 ). 19 in2a logic input control 2a logic input control of out2a (refer to table 6, truth table , page 9 ). 20 lgnd logic ground low-current logic signal ground. vdd in1b out1a vm1 cres c2h psave out2a pgnd1 in1a lgnd vm2 out2b pgnd2 out1b c2l c1l c1h in2a in2b 4 5 6 7 8 9 10 2 3 20 18 14 13 12 11 17 16 15 19 1
analog integrated circuit device data 4 freescale semiconductor 17531a terminal connections figure 4. 17531a, 24-terminal qfn connections table 2. 17531a, 24-terminal qfn definitions a functional description of each terminal can be found in the functional terminal description section beginning on page 10 . terminal number terminal name formal name definition 1, 6, 7, 17 nc no connect this terminal is not used. 2 psave power save logic input controlling power save mode. 3 out2a h-bridge output 2a output a of h-bridge channel 2. 4 pgnd1 power ground 1 high-current power ground 1. 5 out1a h-bridge output 1a output a of h-bridge channel 1. 8 vm1 motor drive power supply 1 positive power source connection for h-bridge 1 (motor drive power supply). 9 c res predriver power supply internal triple charge pump out put as pre-driver power supply. 10 c2h charge pump 2h charge pump bucket capacitor 2 (positive pole). 11 c1h charge pump 1h charge pump bucket capacitor 1 (positive pole). 12 c1l charge pump 1l charge pump bucket capacitor 1 (negative pole). 13 c2l charge pump 2l charge pump bucket capacitor 2 (negative pole). 14 out1b h-bridge output 1b output b of h-bridge channel 1. 15 pgnd2 power ground 2 high-current power ground 2. 16 out2b h-bridge output 2b output b of h-bridge channel 2. 18 vm2 motor drive power supply 2 positive power source connection for h-bridge 2 (motor drive power supply). 19 in2b logic input control 2b logic input control of out2b (refer to table 6, truth table , page 9 ). 20 in2a logic input control 2a logic input control of out2a (refer to table 6, truth table , page 9 ). 21 lgnd logic ground low-current logic signal ground. 22 v dd logic supply control circuit power supply terminal. 23 in1a logic input control 1a logic input control of out1a (refer to table 6, truth table , page 9 ). 24 in1b logic input control 1b logic input control of out1b (refer to table 6, truth table , page 9 ). nc psave out2a pgnd1 out1a nc nc vm1 cres c2h c1h c1l c2l out1b pgnd2 out2b nc vm2 in2b in2a lgnd vdd in1b in1a 1 2 3 4 5 6 789101112 13 14 15 16 17 18 19 20 21 22 23 24 mpc17530ep transparent top view of package
analog integrated circuit device data freescale semiconductor 5 17531a maximum ratings maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit motor supply voltage v m -0.5 to 11.0 v charge pump output voltage v c res -0.5 to 14.0 v logic supply voltage v dd -0.5 to 5.0 v signal input voltage v in -0.5 to v dd + 0.5 v driver output current continuous peak (1) i o i opk 0.7 1.4 a esd voltage human body model (2) machine model (3) v esd1 v esd2 1200 150 v operating junction temperature t j -20 to 150 c operating ambient temperature t a -20 to 65 c storage temperature range t stg -65 to 150 c thermal resistance (4) r ja 50 c/w power dissipation (5) wmfp qfn p d 1.0 2.5 w terminal soldering temperature (6) t solder 260 c notes 1. t a = 25 c. pulse width = 10 ms at 200 ms intervals. 2. esd1 testing is performed in accor dance with the human body model (c zap = 100 pf, r zap = 1500 ). 3. esd2 testing is performed in acco rdance with the machine model (c zap = 200 pf, r zap = 0 ). 4. for qfn only, mounted on 37 x 50 cu area (1.6 mm fr-4 pcb). 5. t a = 25 c. 6. terminal soldering temperature limit is for 10 seconds maximum duration. not designed for i mmersion soldering. ex ceeding these limits may cause malfunction or permanent damage to the device.
analog integrated circuit device data 6 freescale semiconductor 17531a static electrical characteristics static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions t a = 25 c, v dd = 3.0 v, v m = 5.0 v, gnd = 0 v unless other wise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power input motor supply voltage (using internal charge pump) (7) v m-cp 2.0 5.0 8.6 v motor supply voltage ( v cres applied externally) (8) v m-ncp ? ? 10 v gate drive voltage - motor supply voltage ( v cres applied externally) (9) v cres - v m 5.0 6.0 ? v logic supply voltage v dd 2.7 3.0 3.6 v driver quiescent supply current no signal input power save mode i qm i qm-psave ? ? ? ? 100 1.0 a logic quiescent supply current no signal input (10) power save mode i qvdd i qvdd- psave ? ? ? ? 1.0 1.0 ma operating power supply current logic supply current (11) charge pump circuit supply current (12) i vdd i cres ? ? ? ? 3.0 0.7 ma low v dd detection voltage (13) v dddet 1.0 1.6 2.5 v driver output on resistance (14) r ds(on) ? 0.8 1.2 ohms gate drive gate drive voltage (12) no current load v cres 12 13 13.5 v gate drive ability (internally supplied) i c res = - 1.0 ma v cres load 8.5 9.2 ? v recommended external capacitance (c1l ? c1h, c2l ? c2h, c res ? gnd) c cp 0.01 0.1 1.0 f notes 7. gate drive voltage v c res is generated internally. 2 x v dd + v m must be < v c res max (13.5 v). 8. no internal charge pump used. v c res is applied from an external source. 9. r ds(on) is not guaranteed if v c res - v m < 5.0 v. also, function is not guaranteed if v c res - v m < 3.0 v. 10. i q vdd includes the current to pre-driver circuit. 11. i v dd includes the current to predriver circuit at f in = 100 khz. 12. at f in = 20 khz. 13. detection voltage is defined as when the output becomes high-impedance after v dd drops below the detection threshold. v c res is applied from an external source. 2 x v dd + v m must be < v c res max (13.5 v). 14. i o = 0.7 a source + sink.
analog integrated circuit device data freescale semiconductor 7 17531a static electrical characteristics control logic logic input voltage v in 0 ? v dd v logic inputs (2.7 v < v dd < 3.3 v) high-level input voltage low-level input voltage high-level input current low-level input current psave terminal input current low v ih v il i ih i il i il - psave v dd x 0.7 ? ? -1.0 ? ? ? ? ? 50 ? v dd x 0.3 1.0 ? 100 v v a a a table 4. static electrical characteristics (continued) characteristics noted under conditions t a = 25 c, v dd = 3.0 v, v m = 5.0 v, gnd = 0 v unless other wise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 17531a dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions t a = 25 c, v dd = 3.0 v, v m = 5.0 v, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit input pulse input frequency f in ? ? 200 khz input pulse rise time (15) t r ? ? 1.0 (16) s input pulse fall time (17) t f ? ? 1.0 (16) s output propagation delay time (18) turn-on time turn-off time t plh t phl ? ? 0.1 0.1 0.5 0.5 s charge pump wake-up time (19) t vgon ? 1.0 3.0 ms low-voltage detection time t vdddet ? ? 10 ms notes 15. time is defined between 10% and 90%. 16. that is, the input waveform slope must be steeper than this. 17. time is defined between 90% and 10%. 18. output load is 8.0 dc. 19. c cp = 0.1 f.
analog integrated circuit device data freescale semiconductor 9 17531a timing diagrams timing diagrams figure 5. t plh , t phl , and t pzh timing figure 6. low-voltage detection timing figure 7. charge pump timing 10% 50% outa, outb 90% t plh t phl in1, in2, psave t vdddet 0% v dd i m 50% t vdddet 0.8 v 2.5 v v dddeton v dddetoff 90% (<1.0 a) t vgon v dd v c res 11 v table 6. truth table input output charge pump and low voltage detector psave in1a in2a in1b in2b out1a out2a out1b out2b l l l l l run l h l h l run l l h l h run l h h z z run h x x z z stop h = high. l = low. z = high impedance. x = don?t care. psave terminal is pulled up to v dd with internal resistance.
analog integrated circuit device data 10 freescale semiconductor 17531a functional description introduction functional description introduction the 17531a is a monolithic dual h-bridge ideal for portable electronic applications to control bipolar step motors and brush dc motors such as those found in camera len assemblies, camera shutters, and optical disk drives. the device features an on-board charge pump, as well as built-in shoot-through current pr otection and undervoltage shutdown. the 17531a has four operating modes: forward, reverse, brake, and tri-stated (high impedance). the mosfets comprising the output bridge have a total source + sink r ds(on) 1.2 . the 17531a can simultaneously drive two brush dc motors or one bipolar step motor. the drivers are designed to be pwm?ed at frequencies up to 200 khz. functional terminal description logic supply (vdd) the v dd terminal carries the logic supply voltage and current into the logic sections of the ic. vdd has an undervoltage threshold. if the supply voltage drops below the undervoltage threshold, the output power stage switches to a tri-state condition. when the supply voltage returns to a level that is above the threshold, the power stage automatically resumes normal operation according to the established condition of the input terminals. logic input control (in1a, in1b, in2a, and in2b) these logic input terminals control each h-bridge output. in1a logic high = out1a high. however, if all inputs are taken high, the outputs bridges are both tri-stated (refer to table 6, truth table , page 9 ). power save (psave) the psave terminal is a high = true power save mode input. when psave = high, all h-bridge outputs (out1a, out1b, out2a, and out2b) are tri-stated (high-z), regardless of logic inputs (in1a, in1b, in2a, and in2b) states, and the internal charge pump and low voltage detection current are shut off to save power. h-bridge output (out1a, out1b, out2a, and out2b) these terminals provide connect ion to the outputs of each of the internal h-bridges (see figure 2, 17531a simplified internal block diagram , page 2 ). motor drive power supply (vm1 and vm2) the vm terminals carry the main supply voltage and current into the power sections of the ic. this supply then becomes controlled and/or modulat ed by the ic as it delivers the power to the loads attached between the output terminals. all vm terminals mu st be connected together on the printed circuit board. charge pump (c1l and c1h, c2l and c2h) these two pairs of terminals, the c1l and c1h and the c2l and c2h, connect to the external bucket capacitors required by the internal charge pump. the typical value for the bucket capacitors is 0.1 f. predriver power supply (cres) the cres terminal is the output of the internal charge pump. its output voltage is approximately three times of vdd voltage. the vcres voltage is power supply for the internal predriver circuit of h-bridges. power ground (pgnd) power ground terminals. they must be tied together on the pcb. logic ground (lgnd) logic ground terminal.
analog integrated circuit device data freescale semiconductor 11 17531a typical applications functional terminal description typical applications figure 8 shows a typical application for the 17531a. when applying the gate voltage to the cres terminal from an external source, be sure to connect it via a resistor equal to, or greater than, r g = v c res / 0.02 . the internal charge pump of th is device is generated from the vdd supply; therefore, ca re must be taken to provide sufficient gate-source voltage for the high-side mosfets when v m >> v dd (e.g., v m = 5.0 v, v dd = 3.3 v), in order to ensure full enhancement of the high-side mosfet channels. figure 8. 17531a typical application diagram cemf snubbing techniques care must be taken to protect the ic from potentially damaging cemf spikes induced when commutating currents in inductive loads. typical practice is to provide snubbing of voltage transients via placing a capacitor or zener at the supply terminal (vm) (see figure 9 ). pcb layout when designing the printed circuit board (pcb), connect sufficient capacitance between power supply and ground terminals to ensure proper filter ing from transients. for all high-current paths, use wide co pper traces and shortest possible distances. figure 9. cemf snubbing techniques mcu 17531a 3.3 v gnd c1l c1h c2l c2h c res in1b in2a in2b psave vm vdd out1b out2b out1a in1a out2a 5.0 v nc nc nc nc v c res < 14 v r g > v c res /0.02 0.01 f r g nc = no connect 17531a gnd c1l c1h c2l c2h cres vm vdd out out 17531a 3.3 v gnd c1l c1h c2l c2h cres vm vdd out out 5.0 v 3.3 v 5.0 v
analog integrated circuit device data 12 freescale semiconductor 17531a packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? drawing number listed below. ev (pb-free) suffix 20-lead vmfp plastic package 98asa10816d issue a
analog integrated circuit device data freescale semiconductor 13 17531a packaging package dimensions ev (pb-free) suffix 20-lead vmfp plastic package 98asa10816d issue a
analog integrated circuit device data 14 freescale semiconductor 17531a packaging package dimensions ev (pb-free) suffix 20-lead vmfp plastic package 98asa10816d issue a
analog integrated circuit device data freescale semiconductor 15 17531a packaging package dimensions
analog integrated circuit device data 16 freescale semiconductor 17531a packaging package dimensions ep (pb-free) suffix 24-lead qfn plastic package 98arl10577d issue a
analog integrated circuit device data freescale semiconductor 17 17531a packaging package dimensions ep (pb-free) suffix 24-lead qfn plastic package 98arl10577d issue a
analog integrated circuit device data 18 freescale semiconductor 17531a packaging package dimensions ep (pb-free) suffix 24-lead qfn plastic package case 1508-01 issue a
analog integrated circuit device data freescale semiconductor 19 17531a revision history revision history revision date description of changes 2.0 9/2005 ? implemented revision history page ? converted to freescale format 3.0 2/2008 ? corrected table 2, pin definitions on page 4. 4.0 5/2009 ? corrected note 7, in static el ectrical characteristics table.
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